STAR Conference 2025 at NTU — Poster & Highlights

Dates: 4–5 June 2025

Event: SST STAR Conference, Nottingham Trent University (NTU)

#PhDJourney #NTU #STAR2025 #QAOA #FPGA #QuantumComputing

I attended NTU’s SST STAR Conference (4–5 June 2025) to share progress from my PhD on hardware‑aware simulation of the Quantum Approximate Optimisation Algorithm (QAOA). I presented:

• Abstract: Quantum Optimisation on Reconfigurable Hardware: Simulating QAOA with FPGA (with Amir Pourabdollah and Ahmad Lotfi).

• Poster: FPGA‑Accelerated QAOA Simulation for Scalable Performance.

What I showed

We’re restructuring QAOA simulation to fit FPGA dataflow: precomputing/streaming cost‑Hamiltonian terms, pipelining mixer updates, and mapping kernels to on‑chip BRAM/DSP. The aim is better throughput and energy efficiency than CPU/GPU‑only approaches, with a clean path to multi‑FPGA scaling.

Conversations & takeaways

• Interest in precision choices (fixed vs floating) and how they shape accuracy vs resource usage.

• Memory bandwidth and state‑vector tiling/streaming emerged as key to performance.

• Plans to deliver apples‑to‑apples benchmarks against a GPU baseline at equal circuit depth.

A quick thank-you. Thanks to the organisers and the NTU research community for the feedback and discussions. This event helped refine my benchmarks and clarify the next steps toward a robust, reproducible FPGA baseline for QAOA.

Next steps Complete single‑FPGA throughput/latency benchmarks, run scaling studies (qubits, depth p) vs GPU, and prepare plots for a short follow‑up paper.